Semiconductor memory device
US8045409B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2009 |
| Grant date | Oct 25, 2011 |
| Priority date | — |
| Expiry date | May 5, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a plurality of memory cells that are arranged at intersections of a word line with bit line pairs, a precharge circuit that is arranged for each of the bit line pairs and is configured to precharge each of the bit line pairs, and a Y-switch circuit that is arranged for each of the bit line pairs and is configured to select each of the bit line pairs. The semiconductor memory device further includes a mode switching unit that switches the normal mode and the test mode in accordance with a mode selection signal that is externally supplied, a plurality of individual control units that control operation of each of the precharge circuits in accordance with operation of each of the Y-switch circuits in the normal mode, and a block control unit that collectively turns off all of the precharge circuits in the test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.