Clock data recovery device
US8045664B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 6, 2007 |
| Grant date | Oct 25, 2011 |
| Priority date | — |
| Expiry date | Dec 14, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock/data recovery device 1 comprises a sampler 10, a detector 20, an offset determination part 30, a clock output part 40, and a DA converter 50. The phases of clock signals CK and CKX are adjusted so as to match with the phase of an input digital signal. An offset amount (±Voff) added in the sampler 10 is adjusted so as to match with a peak time of a data transition time distribution of a first signal in a case where a value D(n−1) is HIGH level, and is adjusted so as to match with a peak time of a data transition time distribution of a second signal in a case where the value D(n−1) is LOW level. Either of the clock signals CK and CKX is outputted as the recovered clock signal. Time series data of a digital value D(n) is outputted as the recovered data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.