Interpolative all-digital phase locked loop
US8045670B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2008 |
| Grant date | Oct 25, 2011 |
| Priority date | — |
| Expiry date | Jun 14, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0097
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. An interpolator is coupled to the phase detection circuit for performing a sample rate conversion between the reference clock and the clock derived from the RF clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.