Canonical signed digit multiplier
US8046401B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2006 |
| Grant date | Oct 25, 2011 |
| Priority date | — |
| Expiry date | Jan 23, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5332
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiplier is able to multiply an input data value by a selected constant value in CSD form. The selected constant value has a plurality of pairs of bits, and the multiplier includes multiplexers, each controlled by a respective pair of bits of the selected constant value. Each of the multiplexers has a plurality of inputs, and is connected to receive the input data value, the inverse of the input data value, and all zeros on said inputs, and it is controlled such that it outputs either the input data value, the inverse of the input data value, or all zeros, depending on the values of the respective pair of bits of the selected constant value. Variable shift blocks are each connected to receive an input from a respective one of said multiplexers, and are each adapted to shift their received input by a first bit shift value or a second bit shift value, depending on the values of the respective pair of bits of the selected constant value, wherein the first bit shift value and the second bit shift value differ by 1. The multiplier also includes combination circuitry, for receiving the outputs from the plurality of shift blocks, and for combining the outputs from the plurality of shi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.