FIFO system and operating method thereof
US8046506B2 · kind B2 · utility
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11References
13Claims
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Key dates
| Filing date | Mar 21, 2006 |
| Grant date | Oct 25, 2011 |
| Priority date | — |
| Expiry date | Nov 24, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1663
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
FIFO systems and operating method thereof are provided to transfer data between a first device and a second device. In the FIFO system, a memory controller serves as an interface to access a memory device for storage of the data, and a CPU processes instructions to control the data transfer. Two data FIFOs serve as data buffers for data transactions to and from the first and second devices, and two status FIFOs serve as an instruction buffers for status transactions between the first, second devices and the CPU. A data controller connects the memory controller and the two data FIFOs for direct data delivery therebetween.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.