Reconfigurable paired processing element array configured with context generated each cycle by FSM controller for multi-cycle floating point operation
US8046564B2 · kind B2 · utility
9Cited by
1References
13Claims
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Key dates
| Filing date | Sep 19, 2008 |
| Grant date | Oct 25, 2011 |
| Priority date | — |
| Expiry date | Nov 9, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3896
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques, systems and apparatus are described for providing a processing element (PE) structure forming a floating point unit (FPU)-processing element. Each processing element includes each of two multiplexers (MUXes) to receive data from one or more sources including another PE, and select one value from the received data. The processing element includes an arithmetic logic unit (ALU) in communication with the two multiplexers to receive the selected value from each multiplexer as two input values, and process the received two input values to generate results of the ALU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.