Waiver mechanism for physical verification of system designs
US8046726B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2008 |
| Grant date | Oct 25, 2011 |
| Priority date | — |
| Expiry date | Feb 27, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of waiving verification failures is disclosed. The method generally includes the steps of (A) generating a plurality of circuit error files by performing a plurality of physical verifications on a plurality of circuit designs, the circuit error files containing a plurality of circuit errors of the circuit designs, (B) generating a system error file by performing an additional physical verification on a system design, the system error file containing a plurality of system errors of the system design, the system design incorporating the circuit designs and (C) generating a valid error file by removing the circuit errors from the system error file, the valid error file containing a plurality of valid errors comprising a subset of the system errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.