Germanium FinFETs having dielectric punch-through stoppers
US8048723B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2008 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | Sep 29, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02617
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fine. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.