Fabrication method of two-terminal semiconductor component using trench technology
US8048800B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2009 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | Feb 3, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D48/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a two-terminal semiconductor component using a trench technique is disclosed that includes forming a trench by etching an etching pattern formed on a substrate on which an active layer having impurities added is grown, forming a front metal layer on a front upper surface of the substrate by using an evaporation method or a sputtering method after removing the etching pattern, forming a metal plated layer on the front surface of the substrate on which the front metal layer is formed, polishing a lower surface of the substrate by using at least one of a mechanical polishing method and a chemical polishing method until the front metal layer is exposed, forming a rear metal layer on the polished substrate, and removing each component by using at least one of a dry etching method and a wet etching method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.