ΔΣ modulation circuit and system
US8049651B2 · kind B2 · utility
1Cited by
2References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 13, 2010 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | Jan 13, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/43
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A ΔΣ modulation circuit that includes a first integrator and second integrator coupled in series, a quantizer coupled to an output of the second integrator, a delay device disposed in a feedback path from an output of the quantizer to an input of the first and second integrators, an adder which generates a difference between an output and an input of the quantizer, and a feedback circuit including a delay device which couples an output of the adder to an output of one of the first and second integrators.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.