Standby circuit and method for a display device
US8049696B2 · kind B2 · utility
2Cited by
4References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 2, 2008 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | Jun 24, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2370/12
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A standby circuit and method for a display device is disclosed. A detector detects voltage drop of the first termination resistor of a positive path of a clock channel, and the second termination resistors of a negative path. Upon detecting the voltage drop, a switch controller disconnects the positive path or the negative path that has the detected voltage drop, thereby saving power in the standby mode of the display device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.