Video buffer management
US8049821B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 26, 2007 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | Sep 2, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/4383
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment a video system comprises a first tuner, a first memory buffer coupled to the first tuner to receive a first video signal from the first tuner, a second tuner, a second memory buffer coupled to the second tuner to receive a second video signal from the second tuner, and a controller comprising logic to direct the first video signal from the first memory buffer to an output port, receive a signal to switch the output port from the first memory buffer to the second memory buffer, and in response to the signal, couple the output port to the second memory buffer without disrupting the operations of the first memory buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.