Multilayer chip capacitor and circuit board device including the same
US8050012B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2008 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | Mar 27, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A multilayer chip capacitor including: a capacitor body having a lamination structure where a plurality of dielectric layers are laminated and including a first capacitor part and a second capacitor part arranged according to a lamination direction; first to fourth outer electrodes formed on side surfaces of the capacitor body, the first and third outer electrodes having the same polarity and the second and fourth outer electrodes having the same polarity opposite to that of the first outer electrode; and one or more connection conductor lines formed on an outer surface of the capacitor body and connecting the first outer electrode to the third outer electrode or connecting the second outer electrode to the fourth outer electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.