Dual stage sensing for non-volatile memory
US8050072B2 · kind B2 · utility
1Cited by
5References
20Claims
0Family size
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Key dates
| Filing date | Jun 24, 2009 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | Jan 17, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for accessing a non-volatile memory cell. In some embodiments, a memory block provides a plurality of memory cells arranged into rows and columns. A read circuit is configured to read a selected row of the memory block by concurrently applying a control voltage to each memory cell along the selected row and, for each column, using a respective local sense amplifier and a column sense amplifier to successively differentiate a voltage across the associated memory cell in said column to output a programmed content of the row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.