Non-volatile memory device and method of operation therefor
US8050115B2 · kind B2 · utility
3Cited by
14References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2009 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | Jan 30, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the non-volatile memory device includes a plurality of normal memory cells, and at least one flag memory cell associated with one of the plurality of normal memory cells. A normal page buffer is configured to store data read from one of the plurality of normal memory cells. The normal page buffer includes a main latch storing the read data. A control circuit is configured to selectively change data stored in the main latch during a read operation based on a state of the flag memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.