Clock-data recovery circuit, multi-port receiver including the same and associated methods
US8050372B2 · kind B2 · utility
6Cited by
2References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 15, 2008 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | Jun 13, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0812
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock-data recovery circuit includes a plurality of input ports and a code generation circuit. The plurality of input ports generates sampling clock signals based on digital control codes and samples input data signals based on the sampling clock signals to generate output data signals and phase detection signals, respectively. The code generation circuit generates the digital control codes based on the phase detection signals received from the input ports during a training mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.