Digital phase locked loop with integer channel mitigation
US8050375B2 · kind B2 · utility
13Cited by
12References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2008 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | May 19, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0097
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal with a plurality of phases. A switch is coupled to receive the RF clock, and is operative to select one of the plurality of phases. A phase detection circuit is coupled to the switch and is operable to receive a selected phase and to provide digital phase error samples indicative of a time difference between the reference clock and the selected phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.