All digital phase-locked loop with widely locked frequency
US8050376B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2008 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | Jun 5, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An all-digital phase-locked loop (ADPLL) composed of digital circuits is provided. The ADPLL includes a phase-frequency detector (PFD), a control unit, a digital controlled oscillator (DCO), and a plurality of frequency dividers. A first frequency divider divides a frequency of a feedback signal CKOUT by a natural number M to generate a first output signal CKOUT/M. The PFD generates a decrement signal dn and an increment signal up, based on a phase difference and a frequency between a first reference clock signal CKIN and the first output signal CKOUT/M. The DCO generates a clock signal CKDCO based on the digital control signals. A second frequency divider receives the digital control signals from the control unit and the CKDCO from the DCO and divides the frequency of the CKDCO by a bit number of the digital control signals to generate a feedback signal CKOUT to the first frequency divider.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.