Memory controller, nonvolatile storage device, nonvolatile storage system, and nonvolatile memory address management method
US8051268B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2006 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | Nov 2, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
For address management of a nonvolatile memory, the whole logical address space is divided into logical address ranges (0 to 15), and the physical address space is divided into physical areas (segments (0 to 15)). The logical address ranges are respectively associated with the physical areas (segments) to manage the addresses. The sizes of the logical address ranges are equalized. The size of the physical area (segment (0)) corresponding to the logical address range (0) in which data of high rewrite frequency such as an FAT is expected to be stored is larger than those of the other physical areas, and the logical address ranges and the physical areas are allocated. Alternatively, the sizes of the physical areas are equalized, and the size of the logical address range (0) is set as a smaller one than those of the other logical address ranges. With this, the actual rewrite frequencies of the physical areas (segments) are equal to one another, and consequently the life of the nonvolatile memory can be prolonged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.