Method and apparatus for securing digital information on an integrated circuit during test operating modes
US8051345B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2008 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | Dec 29, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Transitory secrets are secured whether stored in registers or latches, RAM, and/or permanent secrets stored in ROM and/or PROM. One embodiment for securing information on an IC includes entering a test mode and resetting each register in response to entering the test mode of operation and prior to receiving a test mode command. An integrated circuit embodiment includes a test control logic operative to configure the integrated circuit into a test mode and to control the integrated circuit while in the test mode, a set of registers, and a functional reset controller coupled to the test control logic and to the set of registers, operative to receive a reset command from the test control logic and provide the reset command to the set of registers in response to a command to enter the test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.