Serial interface device built-in self test
US8051350B2 · kind B2 · utility
0Cited by
5References
15Claims
0Family size
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Inventor
Key dates
| Filing date | Dec 30, 2008 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | Jan 6, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/333
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.