System and method for optimizing iterative circuit for cyclic redundency check (CRC) calculation
US8051359B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2007 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | Sep 2, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6508
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system for generating CRC code words associated with data ranging up to w-bytes in width to be communicated over a communications channel includes a first plurality of serially coupled code-generation blocks each for generating a CRC value based on data input to each block, respective blocks of the first plurality configured for receiving data inputs having respective byte widths ranging from 2N+M to 2N−L+M, where N is equal to log2(w), and M is an offset value, and L is a whole number based on a maximum propagation delay criteria; a second plurality of parallel coupled code-generation blocks each for generating a CRC value based on data inputs, respective blocks of the second plurality configured for receiving data having respective byte widths ranging from 2N−L−1+M to 20; and, a device for selecting particular CRC code generation blocks in the first and second pluralities to be included in a CRC calculation based on the data input; wherein any number of data input bytes may be processed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.