Modifying integrated circuit layout
US8051400B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 21, 2008 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | Feb 1, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A layout for an integrated circuit includes standard cells positioned at standard cell sites. Programmable cells are positioned at programmable fill sites which have a size sufficient to accommodate the programmable cells and are not occupied by standard cells. The position of these programmable sites is recorded in site data as part of the layout data associated with the layout. Empty standard cell sites remaining after standard cells and programmable cells have been placed are filled with standard fill cells. The boundaries of the programmable cells are not constrained other than by alignment with standard cell sites. This permits a high density of programmable fill sites and programmable cells to be achieved. When it is desired to replace a programmable cell with a programmed cell the programmable cells are all deleted from the layout and then the required programmed cells are subject to an automated placement algorithm to place them where appropriate for their function. The remaining empty programmable fill sites are then refilled with programmable cells. Finally, routing algorithms to connect to and from the newly introduced programmed cells are executed to connect those progr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.