Method of forming a high voltage device
US8053319B2 · kind B2 · utility
1Cited by
5References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2009 |
| Grant date | Nov 8, 2011 |
| Priority date | — |
| Expiry date | Oct 14, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a device is presented. A substrate prepared with an active device region is provided. The active device region includes gate stack layers of a gate stack that includes at least a gate electrode layer over a gate dielectric layer. An implant mask is formed on the substrate with an opening exposing a portion of a top gate stack layers. Ions are implanted through the opening and gate stack layers into the substrate to form a channel well. The substrate is patterned to at least remove portion of a top gate stack layer unprotected by the implant mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.