Capacitorless DRAM and methods of manufacturing and operating the same
US8053822B2 · kind B2 · utility
6Cited by
0References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 22, 2008 |
| Grant date | Nov 8, 2011 |
| Priority date | — |
| Expiry date | Sep 3, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/711
Abstract
Example embodiments provide a capacitorless dynamic random access memory (DRAM), and methods of manufacturing and operating the same. The capacitorless DRAM according to example embodiments may include a semiconductor layer separated from a top surface of a substrate and that contains a source region, a drain region, and a channel region, a charge reserving layer formed on the channel region, and a gate formed on the substrate to contact the channel region and the charge reserving layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.