Stacked gate nonvolatile semiconductor memory and method for manufacturing the same
US8053825B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2007 |
| Grant date | Nov 8, 2011 |
| Priority date | — |
| Expiry date | Mar 3, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/35
Abstract
A stacked gate nonvolatile semiconductor memory includes at least a memory cell transistor and a selective gate transistor which are formed on a semiconductor substrate. The memory cell transistor includes a floating gate made of a semiconductor material below an interlayer insulating layer and a control gate made of a silicide above the interlayer insulating layer. The selective gate transistor includes a semiconductor layer made of the semiconductor material, a silicide layer made of the silicide and a conductive layer made of a conductive material not subject to silicide process which is formed through the interlayer insulating film so as to electrically connect the semiconductor layer and the silicide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.