Field effect transistor (FET) having nano tube and method of manufacturing the FET
US8053846B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2007 |
| Grant date | Nov 8, 2011 |
| Priority date | — |
| Expiry date | Jun 5, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/687
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor includes: a semiconductor substrate; a channel region arranged on the semiconductor substrate; a source and a drain respectively arranged on either side of the channel region; and a conductive nano tube gate arranged on the semiconductor substrate to transverse the channel region between the source and the drain. Its method of manufacture includes: arranging a conductive nano tube on a surface of a semiconductor substrate; defining source and drain regions having predetermined sizes and traversing the nano tube; forming a metal layer on the source and drain regions; removing a portion of the metal layer formed on the nano tube to respectively form source and drain electrodes separated from the metal layer on either side of the nano tube; and doping a channel region below the nano tube arranged between the source and drain electrodes by ion-implanting.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.