Semiconductor device and the method of manufacturing the same
US8053859B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2006 |
| Grant date | Nov 8, 2011 |
| Priority date | — |
| Expiry date | Dec 6, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
Abstract
To provide a semiconductor device that exhibits a high breakdown voltage, excellent thermal properties, a high latch-up withstanding capability and low on-resistance. The semiconductor device according to the invention, which includes a buried insulator region 5 disposed between an n−-type drift layer 3 and a first n-type region 7 above n−-type drift layer 3, facilitates limiting the emitter hole current, preventing latch-up from occurring, raising neither on-resistance nor on-voltage. The semiconductor device according to the invention, which includes a p-type region 4 disposed between the buried insulator region 5 and n−-type drift layer 3, facilitates depleting n−-type drift layer 3 in the OFF-state of the device. The semiconductor device according to the invention, which includes a second n-type region 6 disposed between the first n-type region 7 and the n−-type drift layer 3, facilitates dissipating the heat caused in the channel region or in the first n-type region 7 to a p+-type collector layer 1a, which is a semiconductor substrate, via the second n-type region 6, n−-type drift layer 3 and an n-type buffer layer 2.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.