Non-volatile memory device and page buffer circuit thereof
US8054682B2 · kind B2 · utility
5Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2009 |
| Grant date | Nov 8, 2011 |
| Priority date | — |
| Expiry date | Nov 25, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory device includes a cell array including a plurality of memory cells, a page buffer block controlling bitlines of the plurality of memory cells to program the memory cells to a first target state or a second target state, and a control logic configured to skip a verify operation for the memory cells programmed to the first target state and perform a verify operation for the memory cells programmed to the second target state during a second program loop when the memory cells programmed to the first target state are determined to be in a pass condition during a first program loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.