Flash memory device reducing noise of common source line, program verify method thereof, and memory system including the same
US8054692B2 · kind B2 · utility
25Cited by
3References
20Claims
0Family size
Assignee
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Key dates
| Filing date | May 27, 2009 |
| Grant date | Nov 8, 2011 |
| Priority date | — |
| Expiry date | Jun 25, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory device controls a common source line voltage and performs a program verify method. A plurality of memory cells is connected between a bit line and the common source line. A data input/output circuit is connected to the bit line and is configured to store data to be programmed in a selected memory cell of the plurality of memory cells. The data input/output circuit maintains data to be programmed within the data input/output circuit during a program verify operation, and decreases noise in the common source line by selectively precharging the bit line based on the data to be programmed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.