Parallel rate control for digital video encoder with multi-processor architecture and picture-based look-ahead window
US8054880B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2005 |
| Grant date | Nov 8, 2011 |
| Priority date | — |
| Expiry date | Apr 17, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/23406
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method of operating a multi-processor video encoder by determining a target size corresponding to a preferred number of bits to be used when creating an encoded version of a picture in a group of sequential pictures making up a video sequence. The method includes the steps of calculating a first degree of fullness of a coded picture buffer at a first time, operating on the first degree of fullness to return an estimated second degree of fullness of the coded picture buffer at a second time, and operating on the second degree of fullness to return an initial target sized for the picture. The first time corresponds to the most recent time an accurate degree of fullness of the coded picture buffer can be calculated and the second time occurs after the first time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.