Semiconductor memory system and wear-leveling method thereof
US8055836B2 · kind B2 · utility
3Cited by
3References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2008 |
| Grant date | Nov 8, 2011 |
| Priority date | — |
| Expiry date | Apr 2, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor memory system and wear-leveling method thereof. The semiconductor memory system is comprised of a nonvolatile memory including a plurality of logic blocks each of which is divided into a plurality of entries, a file system detecting a type of data to be stored and allocating the logic block or the entry for storing the data in accordance with the data type, and a translation layer leveling wearing degrees over the logic blocks or the entries in accordance with the data type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.