System having memory device accessible to multiple processors
US8055854B2 · kind B2 · utility
12Cited by
10References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2006 |
| Grant date | Nov 8, 2011 |
| Priority date | — |
| Expiry date | Oct 9, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system having a memory device accessible by a plurality of processors is provided. The system includes a memory device, a first processor, and a second processor. The memory device has a first memory array part and a second memory array part. The first processor predominantly accesses the first memory array part of the memory device and selectively accesses the second memory array part of the memory device. The second processor predominantly accesses the second memory array part of the memory device and selectively accesses the first memory array part of the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.