Error correction system and method
US8055982B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 18, 2008 |
| Grant date | Nov 8, 2011 |
| Priority date | — |
| Expiry date | Sep 9, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0057
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method includes receiving payload data from a data source at error correction code (ECC) logic, where the ECC logic is adapted to process a block of data of a particular size via a plurality of stages. The ECC logic is initialized to a selected stage of the plurality of stages. The selected stage includes an initial value and an initial number of cycles. The initial value and the initial number of cycles are related to a number of symbols of padding data corresponding to a difference in size between the payload data and the block of data. The selected stage is related to a state of the ECC logic as if the number of symbols of padding data had already been processed by the ECC logic. The payload data is processed via the ECC logic beginning with the selected stage to produce parity data related to the payload data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.