Poly resistor on a semiconductor device
US8058125B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2010 |
| Grant date | Nov 15, 2011 |
| Priority date | — |
| Expiry date | Aug 4, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
Abstract
The present disclosure provides a poly resistor on a semiconductor device and a method of fabricating the same. In an embodiment, a poly silicon resistor device is formed by providing a substrate having a first region and a second region. A dummy gate stack is formed on the substrate in the first region, wherein the dummy gate stack has a dummy gate stack thickness extending above the substrate. A poly silicon resister is formed on the substrate in the second region, wherein the poly silicon resistor has a poly silicon resistor thickness extending above the substrate a distance which is less than the dummy gate stack thickness. A dopant is implanted into the substrate in the first region thereby forming a source region and a drain region in the first region of the substrate. The dopant is also implanted into the poly silicon resistor. An inter-level dielectric (ILD) layer is formed on the substrate over the dummy gate stack and also over the poly silicon resistor. The ILD layer is planarized, thereby exposing the dummy gate stack and leaving a portion of the ILD layer over the poly silicon resistor. The dummy gate stack is replaced with a high k metal gate while using the portion o…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.