Trap charge equalizing method and threshold voltage distribution reducing method
US8058187B2 · kind B2 · utility
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5Claims
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Key dates
| Filing date | Jan 5, 2010 |
| Grant date | Nov 15, 2011 |
| Priority date | — |
| Expiry date | Jan 5, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/69
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method reduces a threshold voltage distribution in transistors of a semiconductor memory device, where each transistor includes a nitride liner. The method includes injecting electrons into a charge trap inside and outside the nitride liner of the transistors, and partially removing the electrons injected into the charge trap inside and outside the nitride liner to equalize trapped charges in the transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.