Alternate 4-terminal JFET geometry to reduce gate to source capacitance

US8058674B2 · kind B2 · utility

Assignee

• Moxtek, Inc. · US

Inventors

• Derek Hullinger · Orem, US
• Keith Decker · Pleasant Grove, US

Key dates

• Filing date: Oct 7, 2009
• Grant date: Nov 15, 2011
• Expiry date: Jul 24, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/411

Abstract

A 4-Terminal JFET includes a substrate having a first conduction type and an upper layer having a second, opposite, conduction type over the substrate. A gate and a source are embedded in the upper layer. A gate pad is electrically connected to the gate. A region, which has a first conduction type, is formed in the upper layer and separates the upper layer into two sections. This region reduces the overall capacitance between the gate pad and the source. Reduced overall gate to source capacitance can result in reduced noise amplification in the JFET.