Generating multiple clock phases
US8058914B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2009 |
| Grant date | Nov 15, 2011 |
| Priority date | — |
| Expiry date | Jul 29, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a circuit includes a first circuit input for receiving a first reference signal having a first phase; a second circuit input for receiving a second reference signal having a second phase; a third circuit input for receiving a target phase signal; a circuit output for outputting an output signal; a first multiplying mixer cell (MMC) comprising a first MMC input, a second MMC input, and a first MMC output; a second MMC comprising a third MMC input, a fourth MMC input, and a second MMC output. In an example embodiment, the first circuit input is connected to the first MMC input; the second circuit input is connected to the third MMC input; the third circuit input is connected to the second MMC input and the fourth MMC input; the first MMC output and the second MMC output are combined with each other to provide the circuit output; and the output signal, when present, represents an error signal that is proportional to a phase difference between a phase of the target phase signal and an average of the first and second phases.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.