Patent · US Active

Memory array on more than one die

US8059441B2 · kind B2 · utility

2Cited by

1References

22Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Mohammed H. Taufique · Austin, US
Derwin Jallice · Reston, US
Donald W. McCauley · Lakeway, US
John P. DeVale · Austin, US
Edward A. Brekelbaum · Pflugerville, US
Jeffrey P. Rupley, II · Round Rock, US
Gabriel H. Loh · Bellevue, US
Bryan Black · Austin, US

Key dates

Filing date	Feb 22, 2010
Grant date	Nov 15, 2011
Priority date	—
Expiry date	Feb 22, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.