Three-dimensional memory module architectures
US8059443B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2007 |
| Grant date | Nov 15, 2011 |
| Priority date | — |
| Expiry date | May 22, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments of the present invention are directed to stacked memory modules. In one embodiment of the present invention, a memory module comprises at least one memory-controller layer stacked with at least one memory layer. Fine pitched through vias (e.g., through silicon vias) extend approximately perpendicular to a surface of the at least one memory controller through the stack providing electronic communication between the at least one memory controller and the at least one memory layers. Additionally, the memory-controller layer includes at least one external interface configured to transmit data to and from the memory module. Furthermore, the memory module can include an optical layer. The optical layer can be included in the stack and has a bus waveguide to transmit data to and from the at least one memory controller. The external interface can be an optical external interface which interfaces with the optical layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.