Memory device and memory programming method
US8059467B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2009 |
| Grant date | Nov 15, 2011 |
| Priority date | — |
| Expiry date | Jun 15, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices and/or memory programming methods are provided. A memory device may include: a memory cell array including a plurality of memory cells; a programming unit configured to apply a plurality of pulses corresponding to a program voltage to a gate terminal of each of the plurality of memory cells, and to apply a program condition voltage to a bit line connected with a memory cell having a threshold voltage lower than a verification voltage from among the plurality of memory cells; and a control unit configured to increase the program voltage during a first time interval by a first increment for each pulse, and to increase the program voltage during a second time interval by a second increment for each pulse. Through this, it may be possible to reduce a width of a distribution of threshold voltages of a memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.