Hardware based parallel processing cores with multiple threads and multiple pipeline stages
US8059650B2 · kind B2 · utility
21Cited by
12References
17Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 31, 2007 |
| Grant date | Nov 15, 2011 |
| Priority date | — |
| Expiry date | Jun 6, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/3009
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A pipelined out-of-order process and system for handling data packets in a network device. The process and system are scalable to support throughput in excess of 10 Gbps. The system includes a set of processing cores that offload the table look up operations and similar operations from the central processing unit. The central processing unit receives the requisite data needed for performing forwarding, routing, NAT, firewall maintenance and similar operation on data packets from the set of processing cores.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.