Hardware queue management with distributed linking information
US8059670B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2008 |
| Grant date | Nov 15, 2011 |
| Priority date | — |
| Expiry date | Jan 5, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/90
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A network element including a processor with logic for managing packet queues by way of packet descriptor index values that are mapped to addresses in the memory space of the packet descriptors. A linking memory is implemented in the same integrated circuit as the processor, and has entries corresponding to the descriptor index values. Each entry can store the next descriptor index in a packet queue, to form a linked list of packet descriptors. Queue manager logic receives push and pop requests from host applications, and updates the linking memory to maintain the queue. The queue manager logic also maintains a queue control register for each queue, including head and tail descriptor index values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.