Low cost method of fabrication of vertical interconnections combined to metal top electrodes

US8062976B2 · kind B2 · utility

Assignee

• STMicroelectronics SA

Inventors

• Raffaele Vecchione · Napoli, IT
• Luigi Occhipinti · Ragusa, IT
• Nunzia MALAGNINO · Torre Annunziata, IT
• Rossana Scaldaferri · Sapri, IT
• Maria Viviana Volpe · Pozzuoli, IT

Key dates

• Filing date: Jul 27, 2010
• Grant date: Nov 22, 2011
• Expiry date: Jul 27, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10K71/611

Abstract

A method is for forming a vertical interconnection through a dielectric layer between upper and lower electrically conductive layers of an integrated circuit. The method includes forming an opening through the dielectric layer and placing a solidifiable electrically conductive filler into the opening via a printing technique. The solidifiable electrically conductive filler is solidified to thereby form a solidified electrically conducting filler in the opening. A metallization layer is formed over the dielectric layer and the solidified electrically conducting filler to thereby form the vertical interconnection through the dielectric layer between the upper and lower electrically conductive layers of the integrated circuit.