Self-aligned nano field-effect transistor and its fabrication
US8063451B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2009 |
| Grant date | Nov 22, 2011 |
| Priority date | — |
| Expiry date | Jan 28, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/938
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Our invention discloses a self-aligned-gate structure for nano FET and its fabrication method. One dimension semiconductor material is used as conductive channel, whose two terminals are source and drain electrodes. Gate dielectric grown by ALD covers the area between source electrode and drain electrode, opposite sidewalls of source electrode and drain electrode, and part of upper source electrode and drain electrode. Gate electrode is deposited on gate dielectric by evaporation or sputtering. Total thickness of gate dielectric and electrode must less than source electrode or drain electrode. Gate electrode between source electrode and drain electrode is electrically separated from source and drain electrode by gate dielectric. The fabrication process of this self-aligned structure is simple, stable, and has high degree of freedom. Nearly the whole conductive channel between source electrode and drain electrode is covered by gate electrode, so the control efficiency of the gate over the conductive channel, described as transconductance, can be greatly enhanced. Additionally, there is no restriction on material of gate dielectric or electrode, so the devices' threshold voltage can …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.