On-chip temperature gradient minimization using carbon nanotube cooling structures with variable cooling capacity
US8063483B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2007 |
| Grant date | Nov 22, 2011 |
| Priority date | — |
| Expiry date | Sep 30, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic device comprises a die with at least one defined hot-spot area; and at least one defined intermediate temperature area at a temperature lower than the temperature of the hot-spot area. The device also comprises a cooling structure comprising at least one bundle of first nanotubes for cooling the hot spot area and at least one bundle of additional nanotubes for cooling the intermediate temperature area, and having heat conductivity lower than the bundle of first nanotubes. The heat conductivity of both sets of the nanotubes is sufficient to decrease any temperature gradient between the defined hot spot area, the defined intermediate temperature area, and at least one lower temperature area on the die. The walls of the first nanotubes and the additional nanotubes are surrounded by a heat conducting matrix material operatively associated with the lower temperature area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.