Systems and devices for quantum processor architectures
US8063657B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 12, 2009 |
| Grant date | Nov 22, 2011 |
| Priority date | — |
| Expiry date | Dec 23, 2029 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB82Y10/00
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A quantum processor may employ a heterogeneous qubit-coupling architecture to reduce the average number of intermediate coupling steps that separate any two qubits in the quantum processor, while limiting the overall susceptibility to noise of the qubits. The architecture may effectively realize a small-world network where the average qubit has a low connectivity (thereby allowing it to operate substantially quantum mechanically) but each qubit is within a relatively low number of intermediate coupling steps from any other qubit. To realize such, some of the qubits may have a relatively high connectivity, and may thus operate substantially classically.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.