Low depth programmable priority encoders
US8063659B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2010 |
| Grant date | Nov 22, 2011 |
| Priority date | — |
| Expiry date | Oct 12, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/74
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.