Phase interpolator circuit with two phase capacitor charging
US8063686B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2008 |
| Grant date | Nov 22, 2011 |
| Priority date | — |
| Expiry date | Nov 21, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00052
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In one embodiment of the invention, a method is disclosed to generate a clock output signal with selected phase. The method includes selecting a phase delay for the clock output signal; charging a capacitor with a first weighted current during a first phase input clock, charging the capacitor with a second weighted current during a portion of a second phase input clock, and determining if a voltage across the capacitor is greater than or equal to a threshold voltage to generate a first edge of the clock output signal with the selected phase delay. The first weighted current may have a weighting of N out of M to charge the capacitor with a predetermined rate of change in voltage in response to the selected phase delay. The second weighted current may have a weighting of M out of M to charge the capacitor with a constant rate of change.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.