Semiconductor integrated circuit device
US8064222B2 · kind B2 · utility
27Cited by
10References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 1, 2008 |
| Grant date | Nov 22, 2011 |
| Priority date | — |
| Expiry date | Aug 24, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/141
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A COC DRAM including a plurality of stacked DRAM chips is mounted on a motherboard by using an interposer. The interposer includes a Si unit and a PCB. The Si unit includes a Si substrate and an insulating-layer unit in which wiring is installed. The PCB includes a reference plane for the wiring in the Si unit. The wiring topology between a chip set and the COC DRAM is the same for every signal. Accordingly, a memory system enabling a high-speed operation, low power consumption, and large capacity is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.